Abstract: Midori is an efficient and lightweight block cipher algorithm known for its security, flexibility, and ease of implementation, making it suitable for resource-constrained environments. By analyzing the encryption process of the algorithm, this paper introduces an FPGA implementation scheme. By completing two rounds of Midori-64 encryption iterations in a single clock cycle, the 16-round iterative computation of the algorithm is optimized to 8 rounds, effectively reducing the required number of clock cycles and thereby improving performance. After synthesis in the Xilinx ISE Design Suite 14.7, the final implementation achieves a throughput of 1630.7 Mbps and a frequency of 229.31 MHz. Compared to existing studies, this scheme improves the throughput by 25% and 51%, respectively.