FPGA Implementation of Bipartite Collaborative Encryption Algorithm for SM4 Based on Composite Field

To address the problem of low efficiency in software implementation of SM4 collaborative encryption and decryption algorithm,an FPGA implementation scheme of bipartite collaborative encryption and decryption algorithm for SM4 based on composite field is proposed.To improve the implementation speed and reduce the hardware cost,elements in the S-box are decomposed and inverted in the composite field.Multiplicative triples are utilized to realize bipartite collaborative computation,whose validity is verified on FPGA.With the proposed scheme,maximum clock frequency reaches 130.63MHz,and when excluding the time for bipartite communication,the time for collaborative encryption/decryption is 7.852us,which is 253.56 times faster than that for the software implementation.Totally,7000 logic units are occupied,which is~51.9% lower than those for the extended Euclidean method.Experiment results indicate that the proposed scheme is suitable for the highly real-time scenarios.